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Verilog Conventions

Enterprise Architect supports round-trip engineering of Verilog, where these conventions are used.

Stereotypes

Stereotype

Applies To

See also

asynchronous

Method

Corresponds To: A concurrent process.

enumeration

Inner Class

Corresponds To: An enum type.

initializer

Method

Corresponds To: An initializer process.

module

Class

Corresponds To: A module.

part

Attribute

Corresponds To: A component instantiation.

port

Attribute

Corresponds To: A port.

synchronous

Method

Corresponds To: A sequential process.

Tagged Values

Tag

Applies To

See also

kind

Attribute (signal)

Corresponds To: The signal kind (such as register, bus).

mode

Attribute (port)

Corresponds To: The port mode (in, out, inout).

Portmap

Attribute (part)

Corresponds To: The generic / port map of the component instantiated.

sensitivity

Method

Corresponds To: The sensitivity list of a sequential process.

type

Attribute

Corresponds To: The range or type value of an attribute.

Verilog Toolbox Pages

Access: Diagram | Toolbox : More tools | HDL | Verilog Constructs

Drag these icons onto a diagram to model a Verilog design.

Item

Action

Module

Defines a Verilog Module. A module-stereotyped Class element.

Enumeration

Defines an Enumerated Type. An enumeration element.

Port

Defines a Verilog Port. A port-stereotyped attribute.

Part

Defines a Verilog component instantiation. A part-stereotyped attribute.

Attribute

Defines an attribute.

Procedure

Defines a Verilog process:

  • Concurrent - An asynchronous-stereotyped method
  • Sequential - A synchronous-stereotyped method
  • Initializer - An initializer-stereotyped method

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